Biasing Transistor Switching Circuits

Direct-Coupled Switching Circuit – When a transistor is used as a Biasing Transistor Switching Circuits, it is either biased off to I_C = 0, or biased on to its maximum collector current level. Figure 5-53 illustrates the two conditions. Note that the circuit in Fig, 5-53 is termed a direct-coupled switching circuit, because the signal source is directly connected to the circuit. In Fig. 5-53(a) the negative polarity of the base input voltage (V_S) biases the transistor (Q₁) off. In this case, the only current flowing is the collector base leakage current (I_CBO) which is normally so small that it can be neglected.

The transistor collector-emitter voltage is,

With Q₁ off [Fig. 5-53(a)],

In Fig. 5-53(b) V_S is positive, and it biases Q₁ on to the maximum possible I_C level. The collector current is limited only by the collector supply voltage (V_CC) and the collector resistor (R_C). So,

Now consider Fig. 5-54, which shows the output characteristics and dc load line for the Biasing Transistor Switching Circuits in Fig. 5-53. The load line is drawn by the usual process of plotting point A at (I_C= 0 and V_CE = V_CC), and point B at (V_CE = 0 and I_C = V_CC/R_C).

The 1 kΩ load line shows that, when I_B = 0, I_C is close to zero at,

At this point the transistor is said to be cut off. The region of the characteristics below I_B= 0 is termed the cutoff region. When I_C is at its maximum level, the transistor is said to be saturated, and the collector-emitter voltage is the saturation voltage (V_CE(sat)).

The region of the transistor characteristics at (V_CE(sat)) is termed the saturation region. The region between saturation and cutoff is the active region, which is where a transistor is normally biased for, amplification. From the load line, it is seen that V_CE(sat) is dependent upon the I_C level. For the 2 kΩ load line shown dashed in Fig. 5-54, V_CE(sat) is smaller than for R_C =1 kΩ.

Returning to Fig. 5-53(b), it is seen that I_B is a constant quantity,

Also, the level of I_C depends upon I_B,

The collector current can be determined from Eq. 5-25 (which assumes that V_CE(sat) = 0), and the base current can be calculated from Eq. 5-26. Then, the minimum required current gain for the transistor is,

If the transistor h_FE value is less than the calculated h_FE(1) value, I_C will be lower than the level required for transistor saturation. If the actual h_FE of the transistor is greater than the calculated h_FE(1), I_C tends to be greater than the current level required to saturate the transistor. However, I_C cannot exceed V_CC/R_C. Consequently, an h_FE value larger than h_FE(1) will adjust down to h_FE(1). An h_FE value lower than h_FE(1) cannot adjust up. So, to ensure that the transistor in a switching circuit saturates, it must have an h_FE value equal to or greater than the calculated h_FE(1) for the circuit.

V_CE(sat) is typically 0.2 V for a low-current silicon transistor, while V_BE is typically 0.7 V. Consider the circuit in Fig. 5-53(b) once again. If V_BE = 0.7 V and V_CE(sat) = 0.2 V, the transistor base is 0.5 V more positive than the collector,(see Fig. 5-55). This means that the collector-base junction, which is usually reverse biased, is forward biased when the transistor is in saturation. With the collector-base junction forward biased, fewer charge carriers from the emitter are drawn across to the collector, and the device current gain is lower than normal.

 Capacitor Coupled Switching Circuit:

The base bias circuit in Fig. 5-57 is similar to circuits of that type that have already been considered, with the exception that the transistor is biased into saturation. Although too unpredictable for biasing amplifier circuits, base bias is quite satisfactory for Biasing Transistor Switching Circuits. The transistor in Fig. 5-57 is in a normally-on state with V_CE = V_CE(sat). The capacitor-coupled (pulse waveform) input turns the device off, giving V_CE = V_CC.

The transistor base current Is

The collector current can be determined From Eq. 5-25, and then the minimum required h_FE value can be calculated from Eq. 5-27.

Another type of capacitor-coupled switching circuit is illustrated in Fig. 5-58. In this case, resistor R_B keeps the transistor base-emitter voltage at zero, to ensure that the device is in a normally-off state. The capacitor-coupled input voltage biases the transistor on into saturation.

Switching Circuit Design:

The resistance of R_C for any one of the Biasing Transistor Switching Circuits discussed can be calculated by using the specified V_CC and I_C levels with Eq. 5-25. The transistor h_FE(min) value can be used with I_C to determine the minimum I_B level required for transistor saturation. However, concern about the actual transistor current gain can be avoided by using an h_FE value of 10. It is very unlikely that the transistor will have an h_FE(min) less than 10, so a circuit designed in this way will work with virtually any low-current transistor.

The resistance of R_B for the direct-coupled circuit in Fig. 5-53 is calculated from Eq. 5-26. For the normally-on capacitor-coupled circuit in Fig. 5-57, Eq. 5-28 is used for determining the R_B value.

A different approach must be taken for calculating a suitable resistance for R_B in the normally-off capacitor-coupled circuit in Fig. 5-58. The current that flows through R_B when the transistor is off, and the allowable voltage drop across R_B must be considered, (see Fig. 5-59). The resistor current is the collector-base leakage current (I_CBO), and the maximum voltage drop produced by I_CBO must be much smaller than the normal transistor V_BE level when the device is on. I_CBO at maximum transistor temperature is unlikely to exceed 5 μA, and a V_RB of 0.1 V will normally keep the transistor biased off.  So, a maximum resistance value for R_B is,

Typically, an R_B value of 22 kΩ or lower is suitable for keeping the transistor biased off.