DC Load Line for FET

The DC Load Line for FET circuit is drawn on the device output characteristics (or drain characteristics) in exactly the same way as for a BJT circuit. Refer to the n-channel FET circuit in Fig. 10-1. The source terminal is grounded, the gate is biased via resistor R_G to a negative voltage (-V_G), and the drain terminal is supplied from +V_DD via resistor R_D. The dc load line for this circuit is a graph of drain current (I_D) versus drain-source voltage (V_DS), for a given value of drain resistance and a given supply voltage.

From Fig. 10-1, the drain-source voltage is,

V_DS = (supply voltage) – (voltage drop across R_D)

Substituting V_DD, R_D, and convenient levels of I_D into Eq. 10-1, produces corresponding V_DS and I_D values. These values are then plotted on the device characteristics, and the dc load line is drawn through them.

As already explained, the dc load line represents all corresponding I_D and V_DS levels that can exist in a FET circuit, as represented by Eq. 10-1. A point plotted at V_DS = 16 V and I_D = 10 mA on Fig. 10-2 does not appear on the load line, and so this combination of voltage and current cannot exist in this particular circuit (Fig. 10-1).

Bias Point (Q-Point)

Just as in the case of a BJT circuit, the dc bias point, or quiescent point (Q-point), identifies the device current and terminal voltages when there is no at input signal. When a signal is applied to the gate, I_D varies according to the instantaneous amplitude of the signal, producing a variation in V_DS.

For a FET amplifier circuit, V_DS must remain in the pinch-off region of the characteristics. This means that it must not be allowed to fall below the the device pinch-off voltage (V_p in Fig. 10-3), to avoid going into the channel ohmic region. Therefore, in a FET bias circuit the drain-source voltage should always be a minimum of (V_p + 1 V), as illustrated.

Where an external bias voltage (V_G) is included (as in Fig. 10-1), the pinch-off voltage for that bias level on the device characteristics is (V_p – V_G), (see Fig. 10-3). Consequently, the minimum drain-source voltage may be reduced to,

The bias point for a BJT can be selected half-way along the load line, to give the maximum possible symmetrical output voltage variation. To achieve the same result with a FET, the bias point must be half way between V_DS = V_DD and V_DS = V_p. This is illustrated at Q₁ in Fig. 10-4. When maximum V_DS variations are not required, the FET bias point can be selected at any convenient point on the dc load line (Q₂ in Fig. 10-4), just as in the case of a BJT amplifier.

Effect of Source Resistor:

Figure 10-5(a) shows a circuit that has a resistor (R_S) in series with the FET source terminal, and the supply voltage connected directly to the drain. In this case R_S is the dc load, and Eq. 10-1 is rewritten as,

The dc load line is drawn exactly as discussed.

In Fig. 10-5(b) drain and source resistors R_D and R_S are both present, and the total dc load in series with the FET is (R_D + R_S). For drawing the dc load line, Eq. 10-1 is modified to,