Analysis and Design of Combinational and Sequential circuits

1. Analysis and Design of Combinational circuits:

To design of combinational circuits, the procedure involves the following steps:

1.      Find the required number of inputs and outputs and assign a symbol to each.

2.      Derive the truth table according to given specifications and function.

3.      Using the truth table, obtain simplified Boolean functions for each output as a function of the input variables.

4.      Draw the logic circuit diagram.

To obtain the output Boolean functions from a logic diagram, the procedure involves the following steps:

1.      Label all gate outputs with unique symbols.

2.      Find the Boolean functions for these gates.

To obtain the truth table directly from the logic diagram, the procedure involves the following steps:

1.      Determine the number of input variables in the circuit.

2.      Draw the table for these inputs. There are 2^n combinations for the n input variables (0 to (2^n -1)).

3.      Label the outputs with unique symbols for gates in the circuit.

4.      Obtain the outputs of these gates in the table.

Drawbacks of Combinational circuits:
If you need to design a system that stores and uses previous input and output, then we can not use a combinational circuit because it doesn’t have capability to store any state or depend clock or and time. For these properties you can use Sequential circuits.

2. Analysis and Design of Sequential circuits:
To design of Sequential circuits, the procedure involves the following steps:

1.      Derive the state table and state equations.

2.      Derive the state diagram using the state table.

3.      Reduce states using state reduction technique.

4.      Verify the number of Flip-Flops and type of Flip-Flop to be used.

5.      Derive the excitation equations using the excitation table.

6.      Derive the output function and the Flip-Flop input functions.

7.      Derive the logic functions or equation for each output variable.

8.      Draw the required logic diagram.