Ripple Counter 

A ripple counter is an asynchronous counter where only the first flip-flop is clocked by an external clock. All subsequent flip-flops are clocked by the output of the preceding flip-flop. Asynchronous counters are also called ripple-counters because of the way the clock pulse ripples it way through the flip-flops.

The MOD of the ripple counter or asynchronous counter is 2ⁿ if n flip-flops are used. For a 4-bit counter, the range of the count is 0000 to 1111 (2⁴-1). A counter may count up or count down or count up and down depending on the input control. The count sequence usually repeats itself. When counting up, the count sequence goes from 0000, 0001, 0010, ... 1110 , 1111 , 0000, 0001, ... etc. When counting down the count sequence goes in the opposite manner: 1111, 1110, ... 0010, 0001, 0000, 1111, 1110, ... etc.

The complement of the count sequence counts in reverse direction. If the uncomplemented output counts up, the complemented output counts down. If the uncomplemented output counts down, the complemented output counts up.

There are many ways to implement the ripple counter depending on the characteristics of the flip flops used and the requirements of the count sequence.

• Clock Trigger: Positive edged or Negative edged
• JK or D flip-flops
• Count Direction: Up, Down, or Up/Down

Asynchronous counters are slower than synchronous counters because of the delay in the transmission of the pulses from flip-flop to flip-flop. With a synchronous circuit, all the bits in the count change synchronously with the assertion of the clock. Examples of synchronous counters are the Ring and Johnson counter.

It can be implemented using D-type flip-flops or JK-type flip-flops.

The circuit below uses 2 D flip-flops to implement a divide-by-4 ripple counter (2ⁿ = 2² = 4). It counts down.

Notes:

• Click on CLK (Red) switch and observe the changes in the outputs of the flip flops. The CLK switch is a momentary switch (similar to a door bell switch - normally off).
• PR and CLR are both connected to VCC (set to 1)
• The D flip flop clock has a rising edge CLK input. For example Q0 behaves as follows:
  • The D input value just before the CLK rising edge is noted (Q0₀).
  • When CLK rising edge occurs, Q0 is assigned the previously noted D value (Q0₀).
  • Thus, whenever a rising edge appears at the CLK of the D flip flop, the output Q changes state (or toggles).
• The MOD or number of unique states of this 2 flip flop ripple counter is 4 (2²).
• Simulate and Breadboard the Ripple Counter circuit.
• A Truncated Ripple Counter is used if a MOD of less than 2ⁿ is required. For example, if you want to change the sequence from 3,2,1,0,3,2,1,0 ... to 3,2,0,3,2,0 ...