Bidirectional Shift Register

Bidirectional shift registers are the storage devices which are capable of shifting the data either right or left depending on the mode selected. Figure 1 shows an n-bit bidirectional shift register with serial data loading and retrieval capacity. Initially all the flip-flops in the register are reset by driving their clear pins high. Next R/LÌ… control line is made either low or high in order to opt for either left-shift or right-shift of the data bits, respectively.

Now if R/L̅ = 1, then A₁ gates of all the combinational circuits get activated while the A₂ gates will get disabled at the same time. Due to this, the outputs of each flip-flop appear at the inputs of the very-next flip-flop via OR gate output (except for the last flip-flop FF_n).

For example, Q₁ appears at D₂ via the output of OR gate 1 (O₁), Q₂ appears at D₃ via the output of OR gate 2 (O₂), … and Q_n-1 appears at D_n via the output of OR gate 1 (O_n) (red lines). At this instant if the positive edge of the clock pulse appears, then the outputs of the respective flip-flops reflect their inputs. Thus Q₁ = D₁, Q₂ = Q₁,… and Q_n = Q_n-1. This is nothing but right-shift of the data by a single bit within the register. Following on the same grounds, one can note that for every rising edge of the clock, the data within the register shifts right by a single bit as long as R/L̅ remains high.

On the other hand, if R/L̅ goes low, then A₂ gates of the combinational circuits get enabled while A₁ gates get deactivated. This causes the outputs of each flip-flop to appear at the input pins of the very-previous flip-flop through their OR gate outputs (except the first flip-flop, FF₁). For example, Q_n appears at D_n-1 through the output of OR gate n-1 (O_n-1), … Q₃ appears at D₂ via the output of OR gate 2 (O₂), and Q₂ appears at D₁ via the output of OR gate 1 (O₁). These input bits are latched onto their respective output pins as soon as the leading edge of the clock pulse appears and thus Q_n-1 = Q_n, …Q₂ = Q₃ and Q₁ = Q₂ (green lines). This means that for every clock tick, the data within the register moves left by one bit, provided R/L̅ line is zero.

The working of such bidirectional register can be summarized as in Table I and can be further explained by the output wave forms shown by Figure 2.